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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-08103-1E
Family
FR400 Series VLIW Embedded Microprocessor
MB93423
DESCRIPTION
This specifications describe the implementation of the MB93423, incorporating a processor core (FR403-SoC) designed for embedded applications, which is based on a VLIW (Very Long Instruction Word) architecture (the FR-V architecture) . This processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the "VLIW instruction" on a cycle-by-cycle basis. Also, the processor incorporates the following resources : SDRAM controller (SDRAMC) , interrupt controller (IRC) , DMA controller (DMAC) , asynchronous transfer module (UART) , timer/counter (TIMER/COUNTER) , general-purpose I/O (GPIO) , video display controller (VDC) , video capture controller (VCC) , scaler, audio interface, serial interface (I2C*) , USB interface, and memory stick interface. The VLIW instruction and these resources achieve an excellent cost performance in a complex of high-performance general-purpose processing and media processing, such as multifunction printers, digital cameras, and portable information terminals. * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
PACKAGE
337-ball plastic PFBGA
(BGA-337P-M03)
MB93423
FEATURES
CPU Core * 2-way 240 MHz or 266 MHz VLIW Processor Core * Peak Performance 480 MIPS (Integer operation performance) at 240 MHz 1920 MOPS + 240 MIPS (media operation performance) at 240 MHz 532 MIPS (Integer operation performance) at 266 MHz 2128 MOPS + 266 MIPS (media operation performance) at 266 MHz * 64 32-bit registers (32GR + 32FR) Cache * Instruction cache : 8 Kbyte (2way) , line size 32 byte * Data cache : 8 Kbyte (2way) , line size 32 byte * Cache line replace algorithm : LRU * lnstruction cache preload instruction (ICPL) , Data cache preload instruction (DCPL) support * Cache lock support of both instruction and data for each line * Non-blocking cache (data cache) * Store buffer : 64-byte (data cache) SDRAM Interface * SDRAM in accordance with the PC100 or PC133 standard can be connected. * Changeable 32/16-bit data bus * Four CS (2 support only registered-DIMM) DMAC * Four channels (dual address mode) * Data transfer size is selected from 1, 2, 4 and 32 bytes * Maximum 4G-byte data transfer * Priority is fixed or round robin. * Four external request demand signals (DREQ#[3 : 0]) * 32-byte FIFO is built in each DMA channel * Address update Select from increment, holding and decrement * Circular addressing When the transfer byte count reaches the specified value, the transfer address is reset to the initial value and transfer continues. When internal request is specified while circular addressing is specified, the internal request will be ignored. * 2D addressing When the transfer byte count reaches the specified value, "initial value + AP value" is set to transfer address and transfer continues. Local Bus Interface * 24-bit address / 16-bit or 8-bit data * Can directly connect SRAM, ROM, etc. * The programmable address decoder is built into, and maximum 4 chip select pins are equipped with. * Can specify the bus width by each chip select. (Select from 16 bits or 8 bits) * The programmable wait state generator is built into. Interrupt Controller * Maximum 4 external interrupt factors are input (IRQ3-0) / 11 internal interrupt factors are input : (DMA = 4, Timer = 3, UART = 2 and Error response = 2) * Interrupt factors are mapped in 15 levels of interrupt requests. (Continued) 2
MB93423
UART * 16550 subsets * 2 channels of UART are equipped. * Prescaler to generate baud rate is built into. * Modem control signal external pins (RTS#/CTS#) are equipped (to only channel 0) . Timer * 8254 subsets * 3 channels of 16-bit timer are equipped. * Supports mode 0 (terminal count interrupt) , mode 2 (rate generator) , mode 4 (software trigger strobe) , and mode 5 (hardware trigger strobe) . No other mode is supported. * Supports the binary counter. (BCD counter is not supported.) * One channel of prescaler is mounted on the former steps in the timer block. GPIO * 16-bit general-purpose I/O port is equipped with. (Other peripheral functions and I/O pins are shared.) JTAG * Supports the IEEE1149.1 JTAG Boundary Scan function. Video Output * Progressive or interlaced scan method * 320 to 1920 pixels horizontal resolution, 240 to 1200 pixels vertical resolution * Supports 4 : 2 : 2 YCbCr 8 bits (Time-shared; CbYCrY; conforms to BT.656) , 4 : 2 : 2 YCbCr 16 bits (Cb and Cr output time-shared; Cb precedes Cr) , 4 : 2 : 2 YCbCr 24 bits (Cb and Cr output concurrently; 2 clocks output) , 4 : 4 : 4 RGB 24 bits for output format * Supports 4 : 2 : 2 YCbCr 16 bits (Cb and Cr time-shared; Cb precedes Cr) , 4 : 4 : 4 RGB 24 bits (No filler byte) for input data * Hardware cursor : 1 piece (32 x 32; 2 colors + transparent color) Video Input * Progressive or interlaced scan method * 320 to 1920 pixels horizontal resolution, 240 to 1200 pixels vertical resolution * Supports 4 : 2 : 2 YCbCr 8 bits (Time-shared; CbYCrY; conforms to BT.656) , 4 : 2 : 2 YCbCr 16 bits (Cb and Cr output time-shared; Cb precedes Cr) , 4 : 2 : 2 YCbCr 24 bits (Cb and Cr output concurrently; 2 clocks output) , 4 : 4 : 4 RGB 24 bits for input format * Supports 4 : 2 : 2 YCbCr 16 bits (Cb and Cr time-shared; Cb precedes Cr) , 4 : 4 : 4 RGB 24 bits (No filler byte) for output data * Hardware cursor : 1 piece (32 x 32; 2 colors + transparent color) Scaler * Maximum pixel count in horizontal direction for input image size * Maximum pixel count in vertical direction for input image size * Maximum pixel count in horizontal direction for output image size * Maximum pixel count in vertical direction for output image size : 1920 (brightness component) : 768 : 360 (brightness component) : 288
Audio Output * This is an interface supporting the 3-wire serial (supporting I2S which is MSB-justified) and the PCM highway. * Maximum : 32 bits/sample (I2S which is MSB-justified) * Fixed at 8 bits/sample (PCM highway) * Depends on frequency of supplied clock (Either of the following is supplied from outside : 256/384/512/768 fs.) (Continued)
3
MB93423
(Continued) Audio Input * This is an interface supporting the 3-wire serial (supporting I2S which is MSB-justified) and the PCM highway. Input data is arranged in the front-justified format (starting with MSB) . * Maximum : 32 bits/sample (I2S which is MSB-justified) * Fixed at 8 bits/sample (PCM highway) * Depends on frequency of supplied clock (Either of the following is supplied from outside : 256/384/512/768 fs.) USB * Compliant with USB 2.0 FS function. * V bus and isochronous transfer are not supported. I2C * Standard mode (100 Kbps) and the Fast mode (400 Kbps) are supported. Memory Stick * Compliant with Memory Stick Standard Format Specification ver1.4. * Memory Stick Pro and Memory Stick Duo are supported. (However, excluded Magic Gate function.) AV GPIO * 32 bits (correspond to the pins shared with other functions.) Clock Control * Clock supply can be turned on/off for each unit. Recommended Operation Condition * Power supply voltage : Externally 3.3 V 0.15 V, Internally 1.8 V 0.1 V * Operating temperature range from 0 C to + 70 C
PRODUCT LINEUP
These specifications have indicated two kinds of following products. Part number MB93423BGL-GE1 Core frequency Voltage external / internal Ta Package (Code) Thermal resistance Rth (ja) Remarks 240 MHz 3.3 V 0.15 V / 1.8 V 0.1 V 0 C to + 70 C PFBGA337 (BGA-337P-M03) 45 C/W (0 m/s) Lead-free Solder ball MB93423-26BGL-GE1 266 MHz 3.3 V 0.15 V / 1.8 V 0.1V
4
MB93423
PIN ASSIGNMENT
49 pins from K10 to T16 are for thermal. Connect them to VSS. (TOP-VIEW)
INDEX 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 1 2 3 4 5 6 7 8 9 2 96 3 4 5 93 6 92 7 91 8 90 9 89 10 88 11 87 12 86 13 85 14 84 15 83 16 82 17 81 18 80 19 79 20 78 21 77 22 76 23 75 24 74 25 73
95 94
97 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 72 98 185 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 162 71 99 186 265 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 244 161 70 100 187 266 337 101 188 267 102 189 268 103 190 269 104 191 270
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
318 243 160 69 317 242 159 68 316 241 158 67 315 240 157 66 314 239 156 65 313 238 155 64 312 237 154 63 311 236 153 62 310 235 152 61 309 234 151 60 308 233 150 59 307 232 149 58 306 231 148 57 305 230 147 56 304 229 146 55 303 228 145 54 302 227 144 53
10 105 192 271 11 106 193 272 12 107 194 273 13 108 195 274 14 109 196 275 15 110 197 276 16 111 198 277 17 112 199 278 18 113 200 279 19 114 201 280 20 115 202 281 21 116 203 282
22 117 204 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 226 143 52 23 118 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 142 51 24 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 50 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
(BGA-337P-M03)
5
MB93423
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Position A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11
Pin Name N.C. CLKIN VDDP BS# WE# CS#[3] VCR[7] VCR[3] VSS VCB[5] VCB[1] VSS VDE VDD VCG[3] VCG[1] VDR[5] VSS VDB[7] VDB[3] VDB[0] VSS VDCLKOUT VDE N.C. VDG[5] VDG[6] VDE VDG[1] SDI VSS LRCKI SDA[0] MSINS MSDIO[2]
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Position AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 P25 N25 M25 L25 K25 J25 H25 G25 F25 E25 D25
Pin Name VSS N.C. N.C. TOUT[0] RXD[1] IRQ#[1] VDE DREQ#[3] VDD VDE DDQ[5] DDQ[6] VDE N.C. DDQ[9] DDQ[8] DDQ[12] DDQ[14] DDQM[0] VDE DRAS# VSS DA[5] VSS DCLKFB VSS DA[10] DBA[1] VSS DDQ[16] VDE DDQ[22] VDE DDQ[28] DDQ[30]
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
Position C25 B25 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2
Pin Name DDQ[31] VDE N.C. MTESTMODE RSTOUT# CMODE[1] TESTMODE TDO TDI ERST# VDD D[19] D[21] D[25] D[26] D[28] BE[0] VDE A[4] VSS A[10] A[14] A[16] A[20] A[21] VDE A[22] A[23] VSS RDY# VSS CS#[1] VCR[5] VCR[1] VCB[7] (Continued)
6
MB93423
Pin No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
Position L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23
Pin Name VCB[3] VCHSYNC VSS VCG[5] VSS VDR[7] VDR[3] VDR[1] VDB[5] VDB[2] VDVSYNC ENABLE N.C. VDG[7] VDG[3] VDG[4] VSS TOPFIELD BCKI LRCKO SCL[0] VDE MSDIO VDD N.C. USCKI RXD[0] TXD[1] IRQ#[3] DREQ#[1] MSDIRP# DDQ[1] DDQ[3] DDQ[4] N.C.
Pin No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Position AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 N24 M24 L24 K24 J24 H24 G24 F24 E24 D24 C24 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12
Pin Name DDQ[7] DDQ[11] DDQ[10] VSS DWE# DCS#[0] DCS#[2] DA[1] DA[3] DA[7] VSS DA[8] VDE DA[12] DDQM[2] DDQ[18] DDQ[20] DDQ[24] DDQ[26] VSS VDD N.C. CPUHOLD CMODE[2] CMODE[3] RAMBOOT# TDC TCK ECV VSS D[17] VSS D[23] VSS D[30]
Pin No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Position B11 B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AC4 AC5 AC6 AC7 AC8
Pin Name BE[2] A[2] A[6] A[8] A[12] VDD A[18] A[19] N.C. VDD N.C. RD# ERR# DIR VDE VCR[6] VCR[0] VCB[4] VCVSYNC VCDCLKIN VCG[4] VCG[0] VDR[2] VDB[6] VDHSYNC VDR[0] VDD N.C. VSS VDD N.C. VDG[2] VDG[0] VDPCLKIN DISABLE (Continued) 7
MB93423
Pin No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245
Position AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AB23 AA23 Y23 W23 V23 U23 T23 R23 P23 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 C23
Pin Name SDO SDA[1] MSBS MSCLK UDP VSS TXD[0] VSS MSDIRS# DDQ[2] DREQ#[2] DDQ[0] N.C. VSS VDD N.C. VDE DDQ[15] DDQ[13] DCAS# DCS#[1] DA[2] DA[6] VDDP VDD DBA[0] VDE VSS DDQ[23] DDQ[29] DDQ[21] DDQ[25] N.C. VSS VDD
Pin No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280
Position C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4
Pin Name N.C. PRST# VSS CMODE[0] VDE VSS ECLK D[20] D[24] D[27] D[31] BE[3] A[7] A[11] A[17] A[9] VSS N.C. VSS VSS CS#[2] CS#[0] VCR[4] VCR[2] VDE VCB[6] VCB[2] VCB[0] VCG[7] VCG[6] VCG[2] VDE VDR[6] VDR[4] VDE
Pin No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315
Position Y4 AA4 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AA22 Y22 W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22
Pin Name VDB[4] VDB[1] VSS FSCKI VDDE BCKO SCL[1] VSS XMSCKI MSDIO[1] MSDIO[3] UDM VDE TOUT[1] VDD IRQ#[0] IRQ#[2] DREQ#[0] VSS VSS VSS DDQM[1] VSS DCS#[3] DA[0] VDE DA[4] VDE DCLK DA[9] VSS DA[11] DCKE DDQM[3] DDQ[17] (Continued)
8
MB93423
(Continued) Pin No. 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 Position G22 F22 E22 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 E5 Pin Name DDQ[19] VSS DDQ[27] VSS TRST# TMS HRST# ED D[16] D[18] VDE D[22] VDE D[29] BE[1] VSS A[3] A[5] VDE A[13] A[15] N.C.
Note : The power supply pins are classified as follow. VDD pin is the internal power supply pin. VDDP pin is the analog power supply pin of PLL. VDE pin is the external power supply pin. VSS pin is the ground pin (0 V).
9
MB93423
PIN DESCRIPTION
1. Format
This section explains the pin functions of this LSI chip. The pin function list is in the format shown below : Pin No. Pin Name Direction Type BS Description
Pin Name : Indicates name of external pin If several signals share the same pin, the names are separated by a slash (/) . "XX#" in a signal line name indicates "active low". Direction : Indicates I/O of signal with reference to LSI chip Input Output : Indicates pin for input signal to LSI chip : Indicates pin for output signal from LSI chip
Input/output : Indicates pin for bidirectional signal Type : Indicates pin input/output circuit type Each symbol has the following meaning : Symbol SD TS PU PD OD Description Solid Drive Type of output pin. Normal output. The pin never becomes high impedance. Tri-State Type of output or input/output pin. The pin may become high impedance. Pull-up Type of input pin or input/output pin. A pull-up resistor is built into the circuit. Pull-down Type of input pin or input/output pin. A pull-down resistor is built into the circuit. Open-drain Type of output pin. The pin may become high impedance.
Note : Explains outline of function and relationship with other pins BS : Indicates whether the target of boundary-scan or not.
10
MB93423
2. Local Bus Interface
Pin No. PFBGA 98 97 95 94 183 182 260 93 336 92 335 180 259 91 261 179 258 178 333 89 332 177 256 175 329 86 255 85 84 254 173 327 83 253 82 325 171 324 Pin Name A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] Direction Type BS Description
Output
TS
Yes
Address A word address is output. When the local bus is released, these pins become input.
Input/ output
TS
Yes
Data This is the data bus; D[31] is MSB. When connecting a 16-bit slave device to this signal, connect it to D[31 : 16] (higher) . When connecting a 8-bit slave device to this signal, connect it to D[31 : 24] (higher) .
4
BS#
Output
TS
Yes
Bus Cycle Start This is asserted for only 1 CLKIN cycle at the beginning of a bus cycle to indicate the start of the bus cycle. This pin becomes input when the bus is released. (Continued)
11
MB93423
Pin No. PFBGA
Pin Name
Direction Type
BS
Description Byte Enable This specifies byte lanes for data transfer. BE [0 : 1] is used to access a 16-bit slave device; the correspondence between this signal and the data bus is shown below : BE[0] D [31 : 24] (higher byte) BE[1] D [23 : 16] (lower byte) BE [2] is used to access halfword address. BE [2] A[1] BE [0] is used to access a 8-bit slave device; the correspondence between this signal and the data bus is shown below : BE [0] D [31 : 24] BE [2 : 3] is used to access byte address. BE [2] A[1] BE [3] A[0] These pins become input when the bus is released. To access this LSI as the slave device when this bus is released, it must be treated as a 32-bit slave device. Read This pin is asserted during the second or later CLKIN cycles of read local bus cycles. This pin becomes high impedance when the local bus is released. Write Enable This pin is asserted during a write cycles. It can be used as a strobe pulse for write data. This pin becomes high impedance when the bus is released. Direction Indicates transfer direction of D[31 : 16] pins L : input (read) , H : output (write) This pin becomes input when the bus is released. This LSI determines whether the local bus cycles that performed by external devices are reads or writes, based on the DIR signal. This pin becomes "L" when bus is idle. Ready The bus cycle completion notice from the slave device is input. The value of RDY# is reflected to LCR0.RC at power-on reset. Error This is sampled at the end of the bus cycle; the error notice is input from the slave device to this pin. This pin is ignored when the bus is released. (Continued)
87 330 176 257
BE[0] / BE#[0] BE[1] / BE#[1] BE[2] / BE#[2] BE[3] / BE#[3]
Output
TS
Yes
187
RD#
Output
TS
Yes
5
WE#
Output
TS
Yes
189
DIR
Output
TS
Yes
100
RDY#
Input
Yes
188
ERR#
Input
Yes
12
MB93423
(Continued) Pin No. PFBGA Pin Name Direction Type BS Description Chip Select This signal selects slave device under control of MB93423. The corresponding address is determined from the settings of the programmable address decoder built into MB93423. Connect the boot ROM to the CS#[0] pin.
6 266 102 267
CS#[3] CS#[2] CS#[1] CS#[0]
Output
SD
Yes
13
MB93423
3. SDRAM Interface
Pin No. PFBGA 304 147 231 146 63 236 154 312 62 310 152 150 233 58 307 149 232 148 305 56 230 145 313 Pin Name DCS#[3] DCS#[2] DCS#[1] DCS#[0] DBA[1] DBA[0] DA[12] DA[11] DA[10] DA[9] DA[8] DA[7] DA[6] DA[5] DA[4] DA[3] DA[2] DA[1] DA[0] DRAS# DCAS# DWE# DCKE Direction Type BS Description Chip select This signal is determined by programmable address decoder build into MB93423. DCS#[2] and DCS#[3] are used to specify 168pin registered DIMM. Bank Address The bank address is output.
Output
SD
Yes
Output
SD
Yes
Output
SD
Yes
Multiplexed Address The address multiplexed for SDRAM is output.
Output Output Output Output
SD SD SD SD
Yes Yes Yes Yes
Row Address Strobe Row Address Strobe signal to SDRAM. Column Address Strobe Column Address Strobe signal to SDRAM. Write Enable Write Enable signal to SDRAM. Clock Enable Clock Enable signal to SDRAM. Data Mask These pins (signal) are combined with other signals to specify the byte lane to be written. At read, all the bits are driven Low. The correspondence between this signal and the data bus when connecting 32-bit SDRAM is shown below : DDQM[0] DDQ[31 : 24] DDQM[1] DDQ[23 : 16] DDQM[2] DDQ[15 : 8] DDQM[3] DDQ[7 : 0] The correspondence between this signal and the data bus when connecting 16-bit SDRAM is shown below : DDQM[0] DDQ[31 : 24] DDQM[1] DDQ[23 : 16] (Continued)
54 302 155 314
DDQM[0] DDQM[1] DDQM[2] DDQM[3]
Output
SD
Yes
14
MB93423
(Continued) Pin No. PFBGA 71 70 240 69 318 159 242 158 239 67 241 157 316 156 315 65 228 53 229 52 142 143 50 51 141 47 46 139 138 220 137 222
Pin Name DDQ [31] DDQ[30] DDQ[29] DDQ[28] DDQ[27] DDQ[26] DDQ[25] DDQ[24] DDQ[23] DDQ[22] DDQ[21] DDQ[20] DDQ[19] DDQ[18] DDQ[17] DDQ[16] DDQ[15] DDQ[14] DDQ[13] DDQ[12] DDQ[11] DDQ[10] DDQ[9] DDQ[8] DDQ[7] DDQ[6] DDQ[5] DDQ[4] DDQ[3] DDQ[2] DDQ[1] DDQ[0]
Direction Type
BS
Description
Input/ output
TS
Yes
Data This signal is connected to the SDRAM data bus; DDQ[31] is MSB. When connecting 16-bit SDRAM, connect it to DDQ[31 : 16] When the bus width is set to 16 bits by DCFG.BW, DDQ[15 : 0] is fixed to the high-impedance state.
309
DCLK
Output
SD
Yes
SDRAM Clock This is the output of the clock signal supplied to SDRAM. The output is supplied when MB93423 is in self refresh mode. The output is halted while the PLL is halted. The output is also halted during a power-on reset. Feedback for SDRAM Clock To adjust the DCLK phase, feedback input to the PLL built into this LSI chip.
60
DCLKFB
Input
Yes
15
MB93423
4. General Peripheral Resource
Pin No. PFBGA 296 41 297 134 39 Pin Name IRQ#[0] / PP[0] IRQ#[1] / PP[1] IRQ#[2] / PP[2] IRQ#[3] / PP[3] TOUT[0] / GATE[0] / PP[4] TOUT[1] / GATE[1] / PP[5] RXD[0] / PP[6] Direction Type BS Description Interrupt Request 0 to 3/ GPIO 0 to 3 These pins are used as the interrupt input and as a general-purpose I/O port (GPIO) . Timer ch 0 Output/Timer ch 0 Gate/GPIO 4 This pin is used as the timer ch 0 pin and as a generalpurpose I/O port (GPIO) . Timer ch 1 Output/Timer ch 1 Gate/GPIO 5 This pin is used as the timer ch 1 pin and as a generalpurpose I/O port (GPIO) . UART ch 0 Receive Data/GPIO 6 This pin is used as the UART ch 0 receive data and as a general-purpose I/O port (GPIO) . UART ch 0 Transmit Data/GPIO 7 This pin is used as the UART ch 0 transmit data and as a general-purpose I/O port (GPIO) . Memory Stick Direction Serial/GPIO 8 [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin is used as a general-purpose input port (GPIO) . The output mode must not be used. Memory Stick Direction Parallel/GPIO 9 [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin is used as a general-purpose input port (GPIO) . The output mode must not be used. UART ch 1 Receive Data/GPIO 10 This pin is used as the UART ch 1 receive data and as a general-purpose I/O port (GPIO) . UART ch 1 Transmit Data/GPIO 11 This pin is used as the UART ch 1 transmit data and as a general-purpose I/O port (GPIO) . DMAC ch 0 Request/GPIO 12 This pin is used as the UART ch 0 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 1 Transfer Request/GPIO 15 This pin is used as the DMAC ch 1 transfer request and as a general-purpose I/O port (GPIO) . (Continued)
Input/ output
TS
Yes
Input/ output Input/ output Input/ output Input/ output
TS
Yes
294
TS
Yes
132
TS
Yes
217
TXD[0] / PP[7]
TS
Yes
219
MSDIRS# / PP[8]
Input/ output
TS
Yes
136
MSDIRP# / PP[9]
Input/ output
TS
Yes
40
RXD[1] / PP[10]
Input/ output Input/ output Input/ output Input/ output
TS
Yes
133
TXD[1] / PP[11]
TS
Yes
298
DREQ#[0] / PP[12] DREQ#[1] / PP[15]
TS
Yes
135
TS
Yes
16
MB93423
(Continued) Pin No. PFBGA 221 Pin Name DREQ#[2] / PP[18] DREQ#[3] / PP[19] Direction Type Input/ output Input/ output BS Description DMAC ch 2 Transfer Request/GPIO 18 This pin is used as the DMAC ch 2 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 3 Transfer Request/GPIO 19 This pin is used as the DMAC ch 3 transfer request and as a general-purpose I/O port (GPIO) .
TS
Yes
43
TS
Yes
5. ICE Interface
Pin No. PFBGA Pin Name Direction Type BS Description ESB Reset For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. Hard Reset This is the reset input dedicated to the ICE. This pin function is equivalent to reset by the debugger hardware reset command. Reset by this pin will not reset debug related settings, so this pin can be used for debugging the reset sequence, etc. When using this pin, connect the reset switch signal to this pin; when not using this pin, fix it to the High level. ESB Command Valid Command valid signal for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. ESB Data Data I/O signal for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. ESB Clock Clock signal (output) for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin.
80
ERST#
Input
PD
Yes
322
HRST#
Input
Yes
169
ECV
Input
PU
Yes
323
ED
Input/ output
TS PD
Yes
252
ECLK
Output
TS
Yes
17
MB93423
6. Reset
Pin No. PFBGA Pin Name Direction Type BS Description Power-on Reset This is the level trigger initialization signal. Apply the Low level to this pin for 16 CLKIN clock cycles or more. This pin is used to cause a power-on reset; it initializes all registers and sequencers except cache and GR/FR. Reset Output This signal is asserted during a power-on reset. The power-on reset operation is prolonged in the LSI until the oscillation stabilization wait time for the internal PLL has elapsed. Consequently, use this signal to detect that the power-on reset operation has been completed in the LSI. When HRST# is asserted when the ICE used, this signal (RSTOUT#) is asserted as in the power-on reset. RAM Boot A software reset can be caused by applying a Low level to this pin. When this signal and the PRST# pin are asserted simultaneously, the power-on reset operation is prefered. At a power-on reset, the level input to this pin is reflected in the SA bit of the register HSR0, and then the reset vector address is determined as shown below based on the SA bit. Low level : 0x00000000 High level : 0xFF000000
247
PRST#
Input
Yes
75
RSTOUT#
Output
SD
Yes
166
RAMBOOT#
Input
Yes
7. CPU Status
Pin No. PFBGA 163 Pin Name CPUHOLD Direction Type Output SD BS Yes Description CPU Hold Signal indicating that CPU stops in hold state
8. Clocks
Pin No. PFBGA 2 165 164 76 249 Pin Name CLKIN CMODE[3] CMODE[2] CMODE[1] CMODE[0] Direction Type Input BS Yes Description Clock Input External clock are input to this pin. Clock Mode Determines operating frequency of each section in LSI
Input
Yes
18
MB93423
9. JTAG
Pin No. PFBGA 79 Pin Name Direction Type BS Description Test Data Input This is the test data input pin. This signal is sampled on the rising edge of TCK. Test Data Output This is the test data output pin. This drives active when the ATP controller is the Shift-IR or Shift-DR state. This signal changes on the falling edge of TCK. Test Mode Select This is the test mode select pin. This signal is sampled on the rising edge of TCK. Test ClocK This is the test clock pin. Test Reset This is the TAP controller asynchronous reset. This pin initializes the TAP controller When not using the JTAG function on the printed circuit board, input the same signal as PRST# to this pin.
TDI
Input
PU
No
78
TDO
Output
TS
No
321
TMS
Input
PU
No
168
TCK
Input
PU
No
320
TRST#
Input
PU
No
10. Test
Pin No. PFBGA 77 167 74 Pin Name TESTMODE TDC MTESTMODE Direction Type Input Input Input BS Yes No Yes Description Test Mode Input Fix it at Low level on the printed circuit board. Test Input Fix it at Low level on the printed circuit board. MTEST Mode Input Fix it at Low level on the printed circuit board.
19
MB93423
11. VDC
Pin No. PFBGA 111 278 17 279 112 198 113 201 119 27 26 121 120 207 29 208 19 199 114 281 20 115 282 21 Pin Name VDR[7]/VDCR[7]/AVPP[23] VDR[6]/VDCR[6]/AVPP[22] VDR[5]/VDCR[5]/AVPP[21] VDR[4]/VDCR[4]/AVPP[20] VDR[3]/VDCR[3]/AVPP[19] VDR[2]/VDCR[2]/AVPP[18] VDR[1]/VDCR[1]/AVPP[17] VDR[0]/VDCR[0]/AVPP[16] VDG[7]/VDY[7]/VDX[7] VDG[6]/VDY[6]/VDX[6] VDG[5]/VDY[5]/VDX[5] VDG[4]/VDY[4]/VDX[4] VDG[3]/VDY[3]/VDX[3] VDG[2]/VDY[2]/VDX[2] VDG[1]/VDY[1]/VDX[1] VDG[0]/VDY[0]/VDX[0] VDB[7]/VDCX[7]/VDCB[7]/ AVPP[39] VDB[6]/VDCX[6]/VDCB[6]/ AVPP[38] VDB[5]/VDCX[5]/VDCB[5]/ AVPP[37] VDB[4]/VDCX[4]/VDCB[4]/ AVPP[36] VDB[3]/VDCX[3]/VDCB[3]/ AVPP[35] VDB[2]/VDCX[2]/VDCB[2]/ AVPP[34] VDB[1]/VDCX[1]/VDCB[1]/ AVPP[33] VDB[0]/VDCX[0]/VDCB[0]/ AVPP[32] VDHSYNC/VDHSYNC# Direction Type BS Description R component output / Cr component output / GPIO These pins are display video data output pins. In the RGB mode, the red component is output. In the 24-bit YC mode, Cr component is output. These pins are shared by GPIO unit and set as GPIO input setting after reset. G Component output / Y component output / YC multiplexed output These pins are display video data output pins. In the RGB mode, the green component is output. Also, in the 16-bit or 24-bit YC mode, the Y component is output. When 8-bit YC mode is selected, multiplexed pixel data is output.
Input/ output
TS
Yes
Output
TS
Yes
Input/ output
TS
Yes
B Component output / C component output / Cb component output / GPIO These pins are display video data output pins. In the RGB mode, the blue component is output. In the 16-bit YC mode, the Cb component and the Cr component are time-shared and output. Moreover, in the 24-bit YC mode, Cb component is output. These pins are shared by GPIO unit and set as GPIO input setting after reset.
200
Output
TS
Yes
Horizontal synchronous signal output This pin is for display synchronous signal output. Its polarity is programmable. Vertical synchronous signal output This pin is for display synchronous signal output. Its polarity is programmable. Display pixel clock input This pin inputs a basic clock to generate display pixel clock output. Display pixel clock output Pixel data is output in synchronization with this signal. (Continued)
116
VDVSYNC/VDVSYNC#
Output
TS
Yes
209
VDPCLKIN
Input
Yes
23
VDCLKOUT
Output
TS
Yes
20
MB93423
(Continued) Pin No. PFBGA 117 Pin Name Direction Type BS Description Pixel output enable This signal shows that effective pixel data is output. Its polarity is programmable. Top field This pin shows that the top field is displayed. Its polarity is programmable. Video output disable When this signal is asserted, VDR[7 : 0] / VDCR[7 : 0], VDG[7 : 0] / VDY[7 : 0], VDB[7 : 0] / VDCX[7 : 0] / VDCB[7 : 0], VDHSYNC, VDVSYNC and VDCLKOUT go in to the high impedance state. However, ordinary operation continues inside.
ENABLE/ENABLE#
Output
TS
Yes
123
TOPFIELD/TOPFIELD#
Output
TS
Yes
210
DISABLE
Input
Yes
21
MB93423
12. VCC
Pin No. PFBGA 7 191 103 268 8 269 104 192 274 275 109 196 15 276 16 197 105 271 10 193 106 272 11 273 Pin Name VCR[7]/VCCR[7]/AVPP[15] VCR[6]/VCCR[6]/AVPP[14] VCR[5]/VCCR[5]/AVPP[13] VCR[4]/VCCR[4]/AVPP[12] VCR[3]/VCCR[3]/AVPP[11] VCR[2]/VCCR[2]/AVPP[10] VCR[1]/VCCR[1]/AVPP[9] VCR[0]/VCCR[0]/AVPP[8] VCG[7]/VCY[7]/VCX[7] VCG[6]/VCY[6]/VCX[6] VCG[5]/VCY[5]/VCX[5] VCG[4]/VCY[4]/VCX[4] VCG[3]/VCY[3]/VCX[3] VCG[2]/VCY[2]/VCX[2] VCG[1]/VCY[1]/VCX[1] VCG[0]/VCY[0]/VCX[0] VCB[7]/VCCX[7]/VCCB[7]/ AVPP[31] VCB[6]/VCCX[6]/VCCB[6]/ AVPP[30] VCB[5]/VCCX[5]/VCCB[5]/ AVPP[29] VCB[4]/VCCX[4]/VCCB[4]/ AVPP[28] VCB[3]/VCCX[3]/VCCB[3]/ AVPP[27 VCB[2]/VCCX[2]/VCCB[2]/ AVPP[26] VCB[1]/VCCX[1]/VCCB[1]/ AVPP[25] VCB[0]/VCCX[0]/VCCB[0]/ AVPP[24] VCHSYNC/VCHSYNC# Direction Type BS Description R component input / Cr component input / GPIO These pins are capture video data input pins. In the RGB mode, the red component is input. In the 24-bit YC mode, Cr component is input. These pins are shared by GPIO and set as GPIO input setting after reset. G Component input / Y component input / YC multiplexed input These pins are capture video data input pins. In the RGB mode, the green component is input. Also, in the 24-bit YC mode, the Y component is input. When 8-bit YC mode is selected, multiplexed pixel data is output.
Input/ output
TS
Yes
Input
Yes
Input/ output
TS
Yes
B component input / C component input / Cb component input / GPIO These pins are capture video data input pins. In the RGB mode, the blue component is input. Also, in the 16-bit YC mode, Cb component and Cr component are timeshared and input. Moreover, in the 24-bit YC mode, Cb component is input. These pins are shared by GPIO unit and set as GPIO input setting after reset.
107
Input
Yes
Horizontal synchronous signal input This pin is a capture synchronous signal input pin. Its polarity is programmable. Vertical synchronous signal input This pin is a capture synchronous signal input pin. Its polarity is programmable. Capture pixel clock input This pin is a sampling clock for capture. The edge to use is programmable.
194
VCVSYNC/VCVSYNC#
Input
Yes
195
VCDCLKIN
Input
Yes
22
MB93423
13. Audio
Pin No. PFBGA 211 Pin Name SDO/DX Direction Type Output TS BS Yes Description Audio data output Audio serial data is output. LR clock output / CH0 synchronous signal When performing output that supports I2S or MSB-justified, the LR clock is output. Also, when performing output that supports the PCM highway, the CH0 synchronous signal (FS0) is output. Bit clock output This pin is an audio signal I/O bit clock output pin. I/O that supports the PCM highway always operates in the master mode. Consequently, MCLK that is output by MB93423 is used for audio signal input. Audio data input This pin is for audio serial data input. LR clock input / CH1 synchronous signal output When performing input that supports I2S or MSB-justified, this pin becomes an LR clock input pin. Also, when performing I/O that supports the PCM highway, the CH1 synchronous signal (FS1) is output. Bit clock input This pin inputs bit clocks used for audio signal input that supports I2S or MSB-justified. Basic clock input for audio output This pin inputs the basic clocks (256/384/512/756 fs) for generating bit clocks and LR clocks of audio signal output that supports I2S or MSB-justified and for generating MCLK, FS0, and FS1 of audio signal output that supports the PCM highway.
125
LRCKO/FS0
Output
SD
Yes
286
BCKO/MCLK
Output
SD
Yes
30
SDI/DR
Input
Yes
32
LRCKI/FS1
Input/ output
TS
Yes
124
BCKI
Input
Yes
284
FSCKI
Input
Yes
14. USB/USB-Host
Pin No. PFBGA 215 292 Pin Name UDP UDM Direction Type Input/ output Input/ output Input TS TS BS No No Description USB D+ signal This pin is for differential signal (+) of USB function USB D- signal This pin is for differential signal (-) of USB function USB clock input This pin inputs 48 MHz clock that is required by USB interface.
131
USCKI
Yes
23
MB93423
15. I2C
Pin No. PFBGA 287 126 Pin Name Direction Type BS Description I2C clock These pins are used for a clock signal of the I2C bus. SCL[0] corresponds to I2C channel 0; SCL[1] corresponds to I2C channel 1. I2C data These pins are used for data signals for the I2C bus. SDA[0] corresponds to I2C channel 0; SDA[1] corresponds to I2C channel 1.
SCL[1] SCL[0]
Input/ output
OD
No
212 33
SDA[1] SDA[0]
Input/ output
OD
No
Note : An I/O driver of I2C for MB93423 omits output through rate control. For this reason, the output through rate standard in the Fast mode (400 Kbps) of the I2C bus is not satisfied. Since the standard for the Standard mode (100 Kbps) of the I2C bus is satisfied, it is connectable with the chip which is supporting Standard mode in the Standard mode. If it is connection with the chip of Standard mode down compatible, connection in the Fast mode is also possible.
24
MB93423
16. MS
Pin No. PFBGA Pin Name Direction Type BS Description Memory stick clock input [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin should be pulled up on a board. Memory stick bus state signal [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin should be open state on a board. Memory stick clock output [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin should be open state on a board. Memory stick serial data signal [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin should be open state on a board. Memory stick serial data signal [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] These pins should be open state on a board. Memory stick insert detection signal [Memory stick licensees] Customers are advised to consult with our sales representatives, if you use MS interface. [Non-licensees] This pin should be open state on a board.
289
XMSCKI
Input
Yes
213
MSBS
Output
SD
Yes
214
MSCLK
Output
SD
Yes
128
MSDIO/MSDIO[0]
Input/ output
PD
Yes
291 35 290
MSDIO[3] MSDIO[2] MSDIO[1]
Input/ output
PD
Yes
34
MSINS
Input
Yes
25
MB93423
PIN STATE
Initial value : Indicates pin state immediately after power-on reset. The meaning of each symbol is given below : Symbol Meaning H L HiZ X Indicates high level Indicates low level Indicates high-impedance state Indicates either high level or low level
Pin Name A[23 : 2] D[31 : 16] BE[0 : 3]/BE#[0 : 3] BS# , RD# , WE# DIR RDY# ERR# CS#[3 : 0] DCS#[3 : 0] DBA[1 : 0] DA[12 : 0] DRAS# , DCAS# DWE# DCKE DDQM[0 : 3] DDQ[31 : 0] DCLK DCLKFB IRQ#[0 : 3]/PP[0 : 3] TOUT[0]/GATE[0]/PP[4] TOUT[1]/GATE[1]/PP[5] RXD[0]/PP[6] TXD[0]/PP[7] MSDIRS#/PP[8] MSDIRP#/PP[9] RXD[1]/PP[10] TXD[1]/PP[11]
Initial State HiZ HiZ HiZ HiZ HiZ H H L X H H H H HiZ L HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ
Core Sleep Mode Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation
Bus Sleep Mode X HiZ X H X HiZ H L X X L H L H HiZ Operation Operation Operation Operation Operation Operation X or HiZ X or HiZ Operation Operation
PLL Operation Mode X HiZ X H X HiZ H L X X L H L H HiZ Operation X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ
PLL Stop Mode X HiZ X H X HiZ H L X X L H L H HiZ L X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ (Continued)
26
MB93423
Pin Name DREQ#[0]/PP[12] DREQ#[1]/PP[15] DREQ#[2]/PP[18] DREQ#[3]/PP[19] ERST# , HRST# ECV ED ECLK PRST# RSTOUT# RAMBOOT# CPUHOLD CLKIN CMODE[3 : 0] TDI TDO TMS , TCK , TRST# TESTMODE , TDC , MTESTMODE VDR[7 : 0]/VDCR[7 : 0]/ AVPP[23 : 16] VDG[7 : 0]/VDY[7 : 0]/VDX[7 : 0] VDB[7 : 0]/VDCX[7 : 0]/ VDCB[7 : 0]/AVPP[39 : 32] VDHSYNC/VDHSYNC# VDVSYNC/VDVSYNC# VDPCLKIN VDCLKOUT ENABLE/ENABLE# TOPFIELD/TOPFIELD# DISABLE VCR[7 : 0]/VCCR[7 : 0]/ AVPP[15 : 8] VCG[7 : 0]/VCY[7 : 0]/VCX[7 : 0] VCB[7 : 0]/VCCX[7 : 0]/ VCCB[7 : 0]/AVPP[31 : 24]
Initial State HiZ HiZ HiZ HiZ HiZ L L L HiZ
Core Sleep Mode Operation Operation Operation Operation HiZ L Operation X HiZ Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation
Bus Sleep Mode X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X X or HiZ X X Operation X X X or HiZ X or HiZ
PLL Operation Mode X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X X or HiZ X X Operation X X X or HiZ X or HiZ
PLL Stop Mode X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X X or HiZ X X Operation X X X or HiZ X or HiZ (Continued) 27
MB93423
(Continued) Pin Name VCHSYNC/VCHSYNC# VCVSYNC/VCVSYNC# VCDCLKIN SDO/DX LRCKO/FS0 BCKO/MCLK SDI/DR LRCKI/FS1 BCKI FSCKI UDP UDM USCKI SCL[1 : 0] SDA[1 : 0] XMSCKI MSBS MSCLK MSDIO/MSDIO[0] MSDIO[3 : 1] MSINS Initial State Core Sleep Mode Operation Operation Operation Operation Operation Operation HiZ HiZ Operation Operation Operation Operation Bus Sleep Mode X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X or HiZ Operation X or HiZ X or HiZ PLL Operation Mode X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X or HiZ Operation X or HiZ X or HiZ PLL Stop Mode X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X or HiZ Operation X or HiZ X or HiZ
28
MB93423
HANDLING DEVICES
* Preventing latch-up MB93423 may suffer latch-up under the following conditions : * A voltage higher than VDE or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VDE pin and VSS pin. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (VDD) to exceed the digital power-supply voltage. * Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. * Power supply pins In products with multiple VDE, VDD or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VDE, VDD and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VDE, VDD and VSS pins near the device. * Pull-up/down resistors The MB93423 does not support internal pull-up/down resistors (except PU/PD Pin Type) . Use external components where needed. * N.C. Pin The N.C. (internally connected) pin must be opened for use.
29
MB93423
BLOCK DIAGRAM
32-bit address AV peripheral controller 32-bit data 32-bit data Strage unit 32-bit address 32-bit data SDRAMC 32-bit data 32-bit address Local bus interface 32-bit data 32-bit data 32-bit address DMAC 32-bit data (4 channels) 32-bit data High-Bandwidth system interconnect (32-bit) 32-bit address Instruction cache (8K Bytes) 32-bit Inst. address 64-bit instruction 32-bit data address 64-bit data Memory protection 64-bit data Media-UNIT FR400 Core Integer-UNIT Instruction fetch Interrupt control Pipe-line control Branch control GR (32 bits x 32 words)
64-bit instruction On-Chip bus interface 32-bit address 32-bit data 32-bit data
32-bit address 64-bit data 64-bit data 64-bit data 64-bit data
64-bit data
64-bit data
Data cache (8K Bytes)
32-bit address Debug support unit 32-bit data 32-bit data
FR (32 bits x 32 words)
C-Unit
Bus bridge
Low-bandwidth peripheral bus (32-bit)
GPIO (16-bit)
Interrupt controller (8 ext. sources+ 11 intl. sources)
Timer (3 channels)
UART (2 channels)
30
MB93423
ELECTRIC CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage (External) * Power supply voltage (Internal) * Power supply voltage (PLL) * Input voltage* Storage temperature * : The parameter is based on VSS = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDE VDD VDDP VI TSTG Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 Max VSS + 4.0 VSS + 2.5 VSS + 2.5 VDE + 0.5 ( 4.0) + 125 Unit V V V V C
2. Recommended Operating Conditions
(VSS = 0 V) Parameter Power supply voltage (External) Power supply voltage (Internal) Power supply voltage (PLL) "L" level input voltage "H" level input voltage Operating temperature VDE VDD VDDP Symbol 240 MHz 266 MHz 240 MHz 266 MHz 240 MHz 266 MHz VIL VIH Ta Value Min 3.15 3.15 1.7 1.7 1.7 1.7 -0.3 2.0 0 Typ 3.3 3.3 1.8 1.8 1.8 1.8 + 25 Max 3.45 3.45 1.9 1.9 1.9 1.9 0.8 VDE + 0.3 + 70 Unit V V V V V V V V C
31
MB93423
USB (VSS = 0 V) Parameter "H" level input voltage "L" level input voltage Differential input sensitivity Differential common mode range "H" level output voltage "L" level output voltage Output signal crossover voltage Bus pull-up/down resistor on upstream port Termination voltage on upstream port pull-up Symbol VIHU VILU VDIU VCMU VOHU VOLU VCRSU Rpu* VTERM Value Min 2.0 0.2 0.8 2.8 0.0 1.3 1.425 3.15 Typ Max 0.8 2.5 3.45 0.3 2.0 1.575 3.45 Unit V V V V V V V k V
* : It is necessary to attach "Rpu" outside. Notes on Board Wiring * For connecting the power supply and ground (GND) , use multiple VDD and VSS pins. The system board based on the MB93423 must be a multi-layer board containing power supply (VDD) and GND (VSS) layers for stable power supply. * Insert sufficient decoupling capacitors (condensers) near the MB93423. Changes to the output levels of many of the output pins on the MB93423 (in particular, those with large load capacitance) may cause variation in power supply. * For those systems which run at a high frequency, low-inductance capacitors and mutual wiring are recommended. Inductance can be lowered by shortening the distance between the processor and decoupling capacitor
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
32
MB93423
3. DC Characteristics
(VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Parameter "L" level input voltage "H" level input voltage "L" level output voltage "H" level output voltage Input leakage current Tri-state output leakage current Power supply current (VDE) Symbol VIL VIH VOL VOH ILI ILZ IOL = 2 mA IOH = -2 mA VIN = 0 or VDE VOUT = 0 or VDE 240 CMODE = 0x9, CLKIN = 60 MHz, MHz (Dhrystone2.1) No Load 266 CMODE = 0x9, CLKIN = 66 MHz, MHz (Dhrystone2.1) No Load 240 CMODE = 0x9, CLKIN = 60 MHz, MHz (Dhrystone2.1) 266 CMODE = 0x9, CLKIN = 66 MHz, MHz (Dhrystone2.1) 240 CMODE = 0x9, CLKIN = 60 MHz, MHz (Dhrystone2.1) 266 CMODE = 0x9, CLKIN = 66 MHz, MHz (Dhrystone2.1) 240 Core sleep mode, MHz CLKIN = 60 MHz 266 Core sleep mode, MHz CLKIN = 66 MHz 240 Bus sleep mode, MHz CLKIN = 60 MHz 266 Bus sleep mode, MHz CLKIN = 66 MHz 240 PLL On mode, MHz CLKIN = 60 MHz 266 PLL On mode, MHz CLKIN = 66 MHz PLL Stop mode, CLKIN = 0 MHz VDE = VI = 0, f = 1 MHz Condition Value Min 0 2.0 0 VDE - 0.4 -5 -5 0 0 Typ 20 22 300 310 3 3 40 40 25 25 12 12 0.5 Max 0.8 VDE 0.4 VDE 5 5 40 44 360 360 6 6 16 Unit V V V V A A mA mA mA mA mA mA mA mA mA mA mA mA mA pF
IDE
Power supply current (VDD)
IDD
Power supply current (VDDP)
IDDP
ICORESLEEP
At sleep power supply current
IBUSSLEEP
IPLLON
IPLLOFF Capacity of pins CPIN
33
MB93423
USB (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Parameter "L" level output voltage "H" level output voltage "L" level output current "H" level output current Output short-circuit current Symbol VOL VOH IOL IOH IOS Conditions IOL = 20 mA IOH = -20 mA VOL = 0.4 V VOH = VDE - 0.4 V Value Min 0 VDE - 0.5 20 -20 Typ Max 0.4 VDE 300 Unit V V mA mA mA
34
MB93423
4. AC Characteristics
(1) Local Bus Interface (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Parameter CLKIN period (TCLKIN) CLKIN high time CLKIN input CLKIN low time CLKIN rise time CLKIN fall time A [23 : 2] D [31 : 16] BE/BE# [0 : 3] BS# Local-bus I/F output RD# WE# DIR RDY# CS# [3 : 0] A [23 : 2] D [31 : 16] Local-bus I/F input BE/BE# [0 : 3] BS# Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Reference Signal Output valid delay time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN fall CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN fall Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise 240 MHz Min 16.7* 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.0 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 Max 30* 1.0 1.0 6.0 6.0 6.0 6.0 6.0 7.0 6.5 6.5 6.5 266 MHz Min 15* 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.0 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 Max 30* 1.0 1.0 6.0 6.0 6.0 6.0 6.0 7.0 6.5 6.5 6.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued) 35
* : Refer to "5. Clock Setting" for details.
MB93423
(Continued) (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Parameter DIR Local-bus I/F input RDY# ERR# Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Reference Signal CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise 240 MHz Min 3.0 1.5 3.0 1.5 3.0 1.5 Max 266 MHz Min 3.0 1.5 3.0 1.5 3.0 1.5 Max Unit ns ns ns ns ns ns
Item
Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF.
setup hold valid valid hold hold
CLKIN Input pin Output pin Input and output pin WE#
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MB93423
(2) SDRAM Interface (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Parameter DCLKFB period (TDCLKFB) DCLKFB high time DCLKFB input DCLKFB low time DCLKFB rise time DCLKFB fall time DCS# [3 : 0] DBA [1 : 0] DA [12 : 0] DRAS# SDRAM I/F output DCAS# DWE# DCKE DDQM [0 : 3] DDQ [31 : 0] SDRAM I/F input DDQ [31 : 0] Reference Signal 240 MHz Min 8.3* 2.5 2.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 15* 1.0 1.0 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 266 MHz Min 7.5* 2.5 2.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 15* 1.0 1.0 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output hold time Input setup time Input hold time DCLKFB rise DCLKFB rise DCLKFB rise
* : This value is decided by CMODE. Notes: * Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less unless otherwise noted. The external output load capacitance is 30 pF unless otherwise noted. * The frequency of the input to DCLKFB and the output from DCLK is decided by the input frequency to CLKIN, and setup of a CMODE [3 : 0] pins. Refer to "5. Clock Setting" for details.
setup hold valid hold
DCLKFB
Output pin
Input and output pin
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MB93423
* This LSI outputs DCLK which is supplied to SDRAM as a clock. PLL is built into this LSI. Adjust the phase of DCLK so that the CLK pin of SDRAM and the internal phase in this LSI may be nearly equal. Therefore, when connecting, adjust the delay time of the feedback path from DCLK to DCLKFB, so that the phase of the clock input to DCLKFB which is the feedback signal to PLL, and the phase of the clock (wave shape on the reception edge of DCLK) input to CLK of SDRAM may be nearly equal.
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MB93423
(3) General Peripheral Resources (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item IRQ# [0 : 3]/ PP [0 : 3] TOUT[0]/ GATE[0]/ PP[4] TOUT[1]/ GATE[1]/ PP[5] RXD[0]/PP[6] TXD[0]/PP[7] MSDIRS#/ PP[8] Resources MSDIRP#/ output PP[9] RXD[1]/PP[10] TXD[1]/PP[11] DREQ# [0]/ PP[12] DREQ# [1]/ PP[15] DREQ#[2]/ PP[18] DREQ#[3]/ PP[19] IRQ#[0 : 3] / PP [0 : 3] TOUT[0]/ Resources GATE[0]/ input PP[4] TOUT[1]/ GATE[1]/ PP[5] Parameter Reference Signal 240 MHz Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 4.0 1.5 4.0 1.5 4.0 1.5 Max 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 266 MHz Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 4.0 1.5 4.0 1.5 4.0 1.5 Max 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued) 39
Output valid delay time CLKIN rise Output hold time CLKIN rise Output valid delay time CLKIN rise Output hold time CLKIN rise
Output valid delay time CLKIN rise Output hold time CLKIN rise
Output valid delay time CLKIN rise Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise
MB93423
(Continued) (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Parameter RXD[0]/PP[6] TXD[0]/PP[7] MSDIRS#/ PP[8] MSDIRP#/ PP[9] RXD[1]/PP[10] Resources input TXD[1]/PP[11] DREQ#[0]/ PP[12] DREQ#[1]/ PP[15] DREQ#[2]/ PP[18] DREQ#[3]/ PP[19] Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Reference Signal CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise 240 MHz Min 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 Max 266 MHz Min 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Item
Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF unless otherwise noted.
setup hold valid hold
CLKIN
Input pin Output pin Input and output pin
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MB93423
(4) ICE Interface (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Parameter ECLK output period ECLK output high time ECLK output ECLK output low time ECLK output rise time ECLK output fall time ICE output ED ERST# HRST# ICE input ECV ED Output hold time Input setup time Input hold time Low pulse width Input setup time Input hold time Input setup time Input hold time Reference Signal ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise 240 MHz Min 30 13.0 13.0 0.0 5.0 0.0 16 5.0 0.0 5.0 0.0 Max 2.0 2.0 8.0 266 MHz Min 30 13.0 13.0 0.0 5.0 0.0 16 5.0 0.0 5.0 0.0 Max 2.0 2.0 8.0 Unit ns ns ns ns ns ns ns ns ns TCLKIN ns ns ns ns
Output valid delay time ECLK rise
Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V and the input level is 0.4 V to 2.4 V. The input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF unless otherwise noted.
setup hold valid hold
ECLK Input pin Input and output pin
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MB93423
(5) Reset (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Reset output Boot input RSTOUT# Parameter Reference Signal 240 MHz Min 0 16 16 Max 8.0 266 MHz Min 0 16 16 Max 8.0 Unit ns TCLKIN TCLKIN
Output valid delay time CLKIN rise Low pulse width Low pulse width
Reset input PRST# RAMBOOT#
(6) CPU Status (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item CPU output CPUHOLD Parameter Reference Signal 240 MHz Min 0 Max 8.0 266 MHz Min 0 Max 8.0 Unit ns
Output valid delay time CLKIN rise
(7) Clocks (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Parameter Input setup time Input hold time Reference Signal 240 MHz Min Max 266 MHz Min Max Unit
Clock CMODE[3 : 0] mode input
Must be fixed to "H" or "L" Must be fixed to "H" or "L"
(8) Test (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item TESTMODE Test mode TDC input MTESTMODE Parameter Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Reference Signal 240 MHz Min Max 266 MHz Min Max Unit
Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L"
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MB93423
(9) Video Display Controller (VDC) (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item VDPCLKIN period VDC clock input VDPCLKIN high time VDPCLKIN low time VDR [7 : 0]/VDCR [7 : 0] VDG [7 : 0]/VDY [7 : 0]/ VDX[7 : 0] VDC I/F output VDB [7 : 0]/VDCX[7 : 0]/ VDCB [7 : 0] VDHSYNC/VDHSYNC# VDVSYNC/VDVSYNC# ENABLE/ENABLE# TOPFIELD/ TOPFIELD# VDCLKOUT* VDC I/F input DISABLE Output hold time Parameter Reference Signal Output valid delay time VDCLKOUT fall 240 MHz/266 MHz Min 12.5 4.0 4.0 -2.0 -2.0 -2.0 -2.0 -2.0 -2.0 -2.0 7.0 2.5 1.5 Max 50 3.0 3.0 3.0 3.0 3.0 3.0 3.0 14.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output hold time Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDPCLKIN rise Input setup time Input hold time VDPCLKIN rise VDPCLKIN rise
* : The falling edge of VDCLKOUT is synchronous with respect to the rising edge of VDPCLKIN. Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V and the input level is 0.4 V to 2.4 V. The external output load capacitance is 30 pF.
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MB93423
(10) Video Capture Controller (VCC) (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item Parameter VCDCLKIN period VCC clock input VCDCLKIN high time VCDCLKIN low time VCR [7 : 0]/VCCR [7 : 0] VCG[7 : 0]/VCY[7 : 0]/ VCX[7 : 0] VCC I/F input Input setup time Input hold time Input setup time Input hold time Reference Signal VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise VCDCLKIN rise 240 MHz/266 MHz Min 12.5 4 4 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 Max 125 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
VCB[7 : 0]/VCCX[7 : 0]/ Input setup time VCCB[7 : 0] Input hold time VCHSYNC/VCHSYNC# VCVSYNC/VCVSYNC# Input setup time Input hold time Input setup time Input hold time
Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V and the input level is 0.4 V to 2.4 V. The external output load capacitance is 30 pF.
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MB93423
(11) Audio (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item FSCKI period FSCKI high time Audio clock FSCKI low time input BCKI period BCKI high time BCKI low time SDO* Audio I/F output LRCKO* BCKO* LRCKI SDI Audio I/F input LRCKI Output valid delay time Output valid delay time Output valid delay time Output valid delay time Input setup time Input hold time Input setup time Input hold time Parameter Reference Signal FSCKI rise FSCKI rise FSCKI rise FSCKI rise BCKI rise BCKI rise BCKI rise BCKI rise 240 MHz/266 MHz Min 25 10.5 10.5 312.5 130 130 3.0 3.0 3.0 3.0 50 50 50 50 Max 10.0 10.0 10.0 10.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* : LRCKO and SDO signals are generated with respect to the falling edge of BCKO (duty 50%) . Note : Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V and the input level is 0.4 V to 2.4 V. The external output load capacitance is 30 pF.
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MB93423
(12) USB Interface (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item USCKI period USB clock input USCKI high time USCKI low time D+/D- rise time USB driver D+/D- fall time Driver output resistance TFR TFF Parameter Reference Signal 240 MHz/266 MHz Min 20 8 8 4 4 90 3 Max 20 20 111.11 19 Unit ns ns ns ns ns %
Differential rise and fall time matching
Notes: * Frequency of USCKI is set to 48 MHz in order to carry out operation based on the standard of USB 2.0 FS. And it is necessary to put in a clock with a frequency accuracy of 2500 ppm. * In order to fulfill the standard of USB 2.0 FS, it is necessary to add 25 to 30 in-series resistance outside.
D+
90%
90%
10%
10% TFR TFF
D-
(13) I2C (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item SCL[1 : 0] I2C I/F output SDA[1 : 0] Parameter Output fall time Output rise time Output fall time Output rise time Reference Signal 240 MHz/266 MHz Min 23* 23* 23* 23* Max 250 300 1000 300 Unit ns ns ns ns
* : 20 + 0.1 x C (C = Capacitance of one bus line in pF) Notes: * Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise noted. * Each voltage value is based on the GND level. The timing measurement reference point is 1.5 V and the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. * The external output load capacitance is 30 pF.
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MB93423
(14) Memory Stick Interface Customers are advised to consult with our sales representatives , if you use MS interface. (15) Power Sequence (VDE = 3.3 V 0.15 V, VDD = VDDP = 1.8 V 0.1 V, VSS = 0 V, Ta = 0 C to + 70 C) Item VDE rise time Power-on VDD rise time Delay time from VDE rise to VDD rise Note : Power-off Sequence is not defined. * Power-on Sequence
VDE - Min
Parameter TRE TRD TDRED
Reference Signal
240 MHz/266 MHz Min -100 Max 30 20 100
Unit ms ms ms
VDE
TRE
TDRED VDD - Min
VDD
TRD
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MB93423
5. Clock Setting
In this LSI, the clock signal inputted into CLKIN is multiplied by internal PLL, and it has distributed to each part in LSI. The multiplication rate for each clock is decided using the CMODE [3 : 0] pins. Depending on this setup, the maximum frequency of CLKIN may be restricted. The maximum frequency that can be inputted into CLKIN and the frequency of each part of LSI are shown below. CMODE Internal operating clock of this LSI Ratio* [0]to[3] CLKIN frequency External 3210 Frequency SDRAM Core bus Core DSU bus 00Ratio* 0 1 0 0 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 Ratio* 0 1 0 1 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 011Ratio* 1 0 0 0 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 Ratio* 1 0 0 1 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 1010 Ratio* 1 0 1 1 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 Ratio* 1 1 0 0 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 Ratio* 1 1 0 1 Freq. MB93423BGL-GE1 [MHz] MB93423-26BGL-GE1 111x1 30.0 33.3 x1 60.0 66.7 x1 30.0 33.3 x1 60.0 66.7 x1 60.0 66.7 x1 60.0 66.7 x1 30.0 33.3 Reserved x1 60.0 66.7 x1 30.0 33.3 Reserved x1 60.0 66.7 x1 60.0 66.7 Reserved x1 30.0 33.3 x1 60.0 66.7 x1 30.0 33.3 Reserved x4 120.0 133.3 x1 60.0 66.7 x2 60.0 66.7 x4 120.0 133.3 x2 60.0 66.7 x4 120.0 133.3 x8 240.0 266.6 x4 240.0 266.6 x8 240.0 266.6 x1 30.0 33.3 x0.5 30.0 33.3 x1 30.0 33.3 x1 60.0 66.7 x2 120.0 133.3 x1 60.0 66.7 x2 120.0 133.3 x2 120.0 133.3 x4 240.0 266.6 x0.25 15.0 16.7 x0.5 30.0 33.3 x1 60.0 66.7 x2 60.0 66.7 x2 120.0 133.3 x4 120.0 133.3 x2 120.0 133.3 x4 120.0 133.3 x0.25 15.0 16.7 x0.5 15.0 16.7
* : "x" indicates the frequency ratio for the external input clock. Notes : * As the setting of CMODE = 0, 1, 2, 3, 6, 7, A, E, F is not confirmed for operation guarantee, do not set them. * By default, the operating frequency of the resource bus clock is the same as that of the external bus. When CLKC.p0 is set to "1", the operating frequency of the resource bus clock is half that of the external bus.
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MB93423
CONNECTION WITH MEMORY
1. Connection with ROM or SRAM
An example of connection between this processor and ROM or SRAM, etc. is shown below. Connection example : when connecting 2 SRAMs (256 K x 8 bits each) to 16-bit bus (The polarity of BE is positive logic.)
MB93423
A [19:2] D [31:24] DIR WE# CS# [n] BE [0] Pull-down in this connection example
A [17:0] I/O [7:0] OE# WE# CS1# CS2
SRAM (1)
A [17:0] D [23:16] Pull-up in this connection example RDY# CS1# BE [1] CS2 I/O [7:0] OE# WE#
SRAM (2)
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MB93423
2. Connection with SDRAM
DCS#[2] and DCS#[3] are only used for connecting the 168-pin registered DIMM. Connect the 168-pin registered DIMM as follows. The DIMM must be "registered". In the registered DIMM, it is assumed that the module connected to DCS#[2] or DCS#[3] is used after DCS#, DBA, DA, DRAS#, DCAS#, DWE#, DDQM, and DCKE are latched once at the rising of DCLK signal. When using DCS#[2] or DCS#[3], the bus width must be set to the 32-bit mode.
MB93423
168 pins Registered-DIMM DBA [1:0] DA [12:0] DCS# [2] DCS# [3] DRAS# DCAS# DWE# DDQM [0:1] BA [1:0] A [12:0] S0# S2# RAS# CAS# WE# DQMB [5:4] DQMB [7:6] DDQM [2:3] DQMB [1:0] DQMB [3:2] DDQ [31:16] DQ [47:32] DQ [63:48] DDQ [15:0] DQ [15:0] DQ [31:16] DCKE DCLK DCLKFB CKE CLK
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MB93423
Example : Connecting Registered-DIMM to DCS#[3 : 2] DCS#[2] and DCS#[3] are only used for connecting the 168-pin registered DIMM. Connect the 168-pin registered DIMM as follows. The DIMM must be "registered". In the registered DIMM, it is assumed that the module connected to DCS#[2] or DCS#[3] is used after DCS#, DBA, DA, DRAS#, DCAS#, DWE#, DDQM, and DCKE are latched once at the rising of DCLK signal. When using DCS#[2] or DCS#[3], the bus width must be set to the 32-bit mode.
MB93423
168 pins Registered-DIMM DBA [1:0] DA [12:0] DCS# [2] DCS# [3] DRAS# DCAS# DWE# DDQM [0:1] BA [1:0] A [12:0] S0# S2# RAS# CAS# WE# DQMB [5:4] DQMB [7:6] DDQM [2:3] DQMB [1:0] DQMB [3:2] DDQ [31:16] DQ [47:32] DQ [63:48] DDQ [15:0] DQ [15:0] DQ [31:16] DCKE DCLK DCLKFB CKE CLK
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MB93423
CONNECTION WITH PERIPHERAL DEVICE
1. Connection with MB93443 (IDE/PC-Card Host Controller)
An example of connection between this processor and peripheral device is shown below 16-bit bus.
Clock Gen.
MB93423 CLKIN CLKIN
MB93443
D [15:00]
D [31:16] A [15:2] BE [0:3] DIR Pull-up is required.
D [31:16] A [15:2] BE [0:3] DIR
BS# RDY#
BS# RDY#
DREQ# [n] (n:0 to 3)
Correspondence is arbitrary.
DREQ# CSC#
CS# [n] (n:Arbitrary except 0) IRQ [n] / PP [n] (n:0 to 3)
Correspondence is arbitrary. Correspondence is arbitrary. Pull-up is required.
CSR# IRQ#
BSTREQ# BSTACK# PRST# PRST#
BW16 Reset Gen.
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MB93423
2. Connection with MB93441 (PCI Bridge Chip)
An example of connection between this processor and peripheral device is shown below 16-bit bus.
Clock Gen.
MB93423 CLKIN Open CLKIN BREQ# BGNT# D [15:0] A [23:16]
MB93441
D [31:16] A [15:2] BE [0:3] DIR Pull-up is required.
D [31:16] A [15:2] BE [0:3] DIR
BS# RDY#
BS# RDY#
DREQ [n] # (n:0 to 3)
Correspondence is arbitrary.
DREQ# CSC#
CS [n] # (n:Arbitrary except 0) IRQ [n] / PP [n] (n:0 to 3)
Correspondence is arbitrary. Correspondence is arbitrary.
CSR# IRQ#
BSTREQ# Pull-up is required. PRST# BSTACK# PRST#
BW16 Reset Gen.
Note : Because address A[23 : 16] is connected to GND as shown in the above figure, it will be short out when MB93441 is a bus master. However, there is no bus slave function and it is prohibited to be a bus master, therefore it will not be short out.
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MB93423
PACKAGE DIMENSION
337-ball plastic PFBGA (BGA-337P-M03)
12.00(.472)REF 0.20(.008) S B B 0.50(.020) TYP
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AE J GECA AC AA W U R N L V T PMK HF DB AD AB Y
13.000.10(.512.004)
A
13.000.10 (.512.004)
12.00(.472) REF 0.50(.020) TYP
3.00(.118) REF
0.20(.008) S A
(INDEX AREA)
3.00(.118) REF 386-o0.300.10 (386-o.012.004)
INDEX
o0.05(.002)
M
S
SAB
0.10(.004) S
0.250.10 (.010.004) (Stand off)
1.150.20 (.045.008) (Seated height)
C
2005 FUJITSU LIMITED B337003S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
54
MB93423
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0505 (c) 2005 FUJITSU LIMITED Printed in Japan

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